The present disclosure relates to a nonvolatile memory accessible in units of a word, a memory controller, a nonvolatile memory accessing method, and a program.
Advances in the miniaturization of process technology for the NAND flash device representative of nonvolatile memories (NVM) have been known to reduce the data retention characteristics of the device. In view of that disadvantage, there has been a need for an error correction code (ECC) capable of providing the device with better error detection and correction than before.
Improved data retention is also one of the key challenges facing the PCRAM (Phase Change Random Access Memory (RAM)) and ReRAM (Resistance RAM), new nonvolatile memories of which the development and commercialization have been advancing in recent years.
Unlike the NAND flash device, the PCRAM and ReRAM can be accessed in units of a word just like the DRAM and SRAM. For that capability, the PCRAM and ReRAM are called NVRAMs (Non Volatile RAM).
The NAND flash device is accessed sequentially at high speed for continuous data. By contrast, the NVRAM is a nonvolatile memory that supports high-speed random access not provided by the NAND flash device.
The NAND flash device is generally used as a storage part in store-and-download (SnD) model applications in which data is read in units of a sector into a work memory for execution.
By contrast, the NVRAM accessible in units of a word allows data therein to be accessed directly by the CPU. For this reason, the NVRAM can be used as a nonvolatile work memory in execute-in-place (XIP) model applications.
To support XIP involves making the most of the primary feature of the NVRAM: its accessibility in units of a word. However, adding an ECC feature to the NVRAM to improve its data retention characteristics as mentioned above can lower access performance of the memory.
Japanese Patent Laid-open No. 2008-84499 (called Patent Document 1 hereunder) discloses a nonvolatile memory furnished with a NAND flash device and configured to improve random access performance.
The NAND flash device-based nonvolatile memory calculates ECC in units of a sector. That means the memory needs to have its data read out in units of at least a sector for error detection and correction purposes. This has lead to the disadvantage of random access being implemented at lower speeds in units of a data size smaller than the sector.
Patent Document 1 proposes performing ECC on data of 32 to 128 bits for error detection and correction in order to improve random access performance with the data smaller in size than the sector.
That is, Patent Document 1 proposes a technique aimed at the NAND flash device of which the memory cells are accessed in units of a page, the technique being used to carry out ECC processing on the data smaller in size than the access unit.